[llvm-dev] Peculiar decision with truncation and CopyToReg

[Nemanja Ivanovic via llvm-dev]

I'm wondering if someone can shed some light on this (conversely, I have to
dig through unfamiliar SDAG code).

The SDAG built out of the following IR inserts a CopyToReg node for
parameter %d into the Entry block SDAG. That is perfectly reasonable.
However, this being an i1 parameter on a target that passes all integers in
wider registers, there needs to be a truncation. The peculiar decision I'm
referring to is that the SDAG chooses to insert the truncation into the
entry block and then CopyToReg that truncated value. In this specific
instance, copying it as a wide integer and then truncating after the
CopyFromReg would produce better code.
So my question is whether this is something that the target can choose
easily or whether this is just the standard approach the SDAG takes and
can't be readily modified.

The IR in question:
define zeroext i1 @_Z18chainedLogicalOps3iiib(i32 signext %a, i32 signext
%b, i32 signext %c, i1 zeroext %d) {
entry:
  %cmp = icmp sgt i32 %a, %b
  %cmp1 = icmp slt i32 %b, 0
  %or.cond = and i1 %cmp, %cmp1
  br i1 %or.cond, label %land.rhs, label %land.end

land.rhs:                                         ; preds = %entry
  %cmp2 = icmp ne i32 %b, %c
  %0 = or i1 %cmp2, %d
  br label %land.end

land.end:                                         ; preds = %land.rhs,
%entry
  %1 = phi i1 [ false, %entry ], [ %0, %land.rhs ]
  ret i1 %1
}

The nodes in the SDAG I am referring to:
              t15: i64,ch = CopyFromReg t0, Register:i64 %vreg5
            t17: i64 = AssertZext t15, ValueType:ch:i1
          t18: i1 = truncate t17
        t24: ch = CopyToReg t0, Register:i1 %vreg8, t18

If t17 was copied and the truncation inserted in 'land.rhs', my target
could make a better ISEL decision.
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