[llvm-dev] Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register

Alex Susu via llvm-dev llvm-dev at lists.llvm.org
Thu Sep 8 06:37:02 PDT 2016

     In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc) 
subregisters per register for my research SIMD processor. I have used so far with success 
32 subregisters.

     However, when using 128 subregisters when I now give the command:
       llvm-tblgen -gen-register-info Connex.td
      I get an error message "error:Ran out of lanemask bits to represent subregister 

     To handle this limitation, I started editing the files where this error comes from:
     More exactly, the error comes from the fact the member LaneMask of the classes 
CodeGenSubRegIndex and CodeGenRegister is unsigned (i.e., 32 bits). So for every 
lane/subregister we require a bit from the type LaneMask.
     I plan to use type long (or even type int1024_t from the boost library, header 
cpp_int.hpp) for LaneMask and change accordingly the methods handing the type.

     Is there are any limitation I am not aware of (maybe in LLVMV's register allocator) 
that would prevent me from using more than 32 lanes/subregisters?

   Thank you very much,

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