[llvm-dev] [RFC] SPARC REX instruction set extension

Daniel Cederman via llvm-dev llvm-dev at lists.llvm.org
Tue Sep 6 04:34:51 PDT 2016

Hello all,

My name is Daniel Cederman and I'm a software engineer at Cobham Gaisler 
working on toolchain support for our LEON3/LEON4 SPARC processors. We at 
Cobham Gaisler have recently designed a new compressed instruction set 
for 32-bit SPARC processors to be used to minimize code size. It is 
called REX and support for it is available in the latest version of our 
LEON3 SPARC processors. A GPL version of the processor VHDL source code, 
with templates for many FPGA:s, is available here: 
http://www.gaisler.com/index.php/downloads/leongrlib. It will be be 
included in GR716, our new rad-hard microcontroller for space 

I have just submitted three patches that will add assembler/disassembler 
support for the REX instruction set extension to the SPARC backend, and 
I would be happy for any comments you might have. I have tried to 
minimize the changes to the common parts of the SPARC backend in hope 
that these patches, and upcoming code generation patches, will be 
accepted into the upstream LLVM repository.


The REX extension was designed to decrease the code size by encoding 
common instructions with a 16-bit representation instead of 32-bit, 
similar to Thumb or Mips16. These shorter instructions comes with the 
cost of only being able to operate on half of the available registers 
and having a reduced or completely removed immediate field.

The new instructions have a binary representation that overlaps that of 
the standard SPARC instructions. For this reason the processor needs to 
enter a special REX mode before they can be used. This is done by 
replacing the SAVE or ADD instruction in the function prologue with one 
of two new 32-bit SPARC instructions, SAVEREX or ADDREX. By entering REX 
mode at the start of a function, using a special instruction, and 
automatically leaving REX mode when making a call to another function, 
it is possible to keep the ABI changes to a minimum. This makes it 
easier to gradually integrate REX code with existing software.

In addition to the new REX instructions it is still possible to use the 
CALL instruction and standard SPARC instructions that follow format 3 
(most instructions except branches, CALL, UNIMP, NOP and SETHI) while in 
REX mode. These are however encoded differently and have to sacrifice a 
part of the immediate (going from 13 to 7 bits). Branches have 
corresponding REX instructions.

A full description of the REX instruction set extension is available at 

A discussion forum for LEON processors is available at 

Best regards,
Daniel Cederman

Daniel Cederman
Software Engineer
Cobham Gaisler

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