[llvm-dev] RFC: Implement variable-sized register classes

[Alex Bradbury via llvm-dev]

On 21 October 2016 at 18:48, Krzysztof Parzyszek
<kparzysz at codeaurora.org> wrote:
> On 10/8/2016 2:52 PM, Alex Bradbury wrote:
>>
>> Have you thought about how the HwMode/variable-sized register class
>> proposal might interact with register AsmNames at all?
>
>
> I just had some time to think about it.  The issue with this is that the
> register names are of interest to the MC layer, while the variable register
> size is handled on the Target level (i.e. TargetRegisterInfo).
>
> Instructions like ADDW and SLLIW still take 64-bit registers in a 64-bit
> mode, but they only access the low 32 bits. In your example, "SLLIW x1, x2,
> 5", both x1 and x2 would be 64-bit registers, but only the low 32 bits of x2
> would be used.  In the assembly source, the names of the 64-bit registers
> would be used, and the instruction semantics (ADD vs ADDW) would be the
> determining factor whether the whole register, or only a part of it is used
> (at least this is how I read the RISC-V spec).

Everything you say makes sense, though the way this situation is
modelled by current in-tree architectures is to have the GPR32
register class contain registers that are subregisters of the GPR64
regs. See the instructions in Mips64InstrInfo.td that take a
GPR32Opnd, or in PPCInstr64Bit.td that take a gprc, It's possible that
it's not really essential to model the distinction between the 64-bit
register with AsmName 'x4' and its 32-bit subregister that also has
AsmName 'x4'. If the distinction isn't important, then obviously
solely relying on the 'HwMode' is sufficient.

Alex