[llvm-dev] Generate Register Indirect mode instruction
Friedman, Eli via llvm-dev
llvm-dev at lists.llvm.org
Wed Oct 12 15:09:23 PDT 2016
On 10/12/2016 2:22 PM, Alex Bradley wrote:
>
>
> > You probably want to look at the x86 backend; it has a lot of
> instructions which involve both computation and memory. Take the
> following IR, a variant of your example:
> >
> > define void @foo(i32 *%a, i32 *%b, i32 *%c) {
> > entry:
> > %0 = load i32, i32* %a, align 4
> > %1 = load i32, i32* %b, align 4
> >
> > %add = add nsw i32 %1, %0
> > store i32 %add, i32* %c, align 4
> > ret void
> > }
> >
> > The x86 backend generates the following:
> >
> > movl (%rsi), %eax
> > addl (%rdi), %eax
> > movl %eax, (%rdx)
> > retq
> >
> > Note in particular the memory operand embedded into the addition.
> >
> > The way the LLVM x86 backend models this is just to pattern match it
> during instruction selection: it matches a pattern like (add r, (load
> addr)) to a single instruction.
>
> Thanks Eli. I will have a look into it. However, the above x86 code
> loads the content of the memory location into eax register and adds
> that register with another memory location.
>
> My target loads the address of the memory locations in the registers
> for both the operands and then uses add operation on the registers in
> an indirect way. How do I specify that in .td files so that it matches
> in ISelDAGToDAG select() function? Any small example?
>
Oh, you mean the result goes into memory, not a register? So, something
like the following:
define void @foo(i32 *%a) {
entry:
%0 = load i32, i32* %a, align 4
%add = add i32 %0, 3
store i32 %add, i32* %a, align 4
ret void
}
On x86, this gets turned into:
addl $3, (%rdi)
retq
From X86InstrArithmetic.td:
// BinOpMI8_RMW - Instructions like "add [mem], imm8".
class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
SDPatternOperator opnode, Format f>
: BinOpMI8<mnemonic, typeinfo, f,
[(store (opnode (load addr:$dst),
typeinfo.Imm8Operator:$src), addr:$dst),
(implicit EFLAGS)]>;
-Eli
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