[llvm-dev] Generate Register Indirect mode instruction

[Alex Bradley via llvm-dev]

Hi All,

I am new to llvm backend. I am trying out few examples to understand
backend codegen. I have ported llvm LEG @
https://github.com/frasercrmck/llvm-leg to llvm 3.9 successfully.

Currently, the LEG instructions are RISC load-store type instruction. I
want to generate some instructions for register indirect mode, like
following:

IR:

@a = local_unnamed_addr global i32 0, align 4
@b = local_unnamed_addr global i32 0, align 4
@c = local_unnamed_addr global i32 0, align 4

; Function Attrs: norecurse nounwind
define void @foo() {
entry:
  %0 = load i32, i32* @a, align 4
  %1 = load i32, i32* @b, align 4
  %add = add nsw i32 %1, %0
  store i32 %add, i32* @c, align 4
  ret void
}


Expected assembly instructions:
MOV R0, #A    // R0 pointing to address of A
MOV R1, #B    // R1 pointing to address of B
ADD *R0, *R1  // Adding both memory operands
MOV #C, *R0  // Moving result to address of C

How should i define such mov and add instruction in my .td files? How will
ISD::LOAD be seleted in ISelDAGtoDAG in select() function? I want to start
with simple .td definitions and would later like to encapsulate them in
multiclass once basic example works.

Can someone please help how to achieve this?

Regards,
Alex
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