[llvm-dev] [RFC] Supporting ARM's SVE in LLVM

[Paul Walker via llvm-dev]

>I haven't seen a similar instruction in SVE yet, but the compulsory
>predicate on all instructions kinda make that redundant, since you can
>always use it to calculate the number of "affected" lanes, and thus
>only increment the "right" amount per iteration and not rely on
>additional instructions. But this also seem to fit the concept of
>"vscale", so if you say:
>
>  %scale = i64 vscale
>
>In RISC-V, this would literally translate to:
>
>  vsetvl t0, a0

>This is one of the issues we have to get right before any IR changes
>are in effect, to make sure we won't need to change it again soon. In
>SVE, such an operation would be a NOP, as the back-end is already
>tracking it via the predicate registers.

SVE has a similar instruction that returns the current vector length (rdvl).  The reason you don’t see it in our example loop’s instruction output is because in that example we are able to use “incw x2” that increments x2 by the number of i32s a vector can hold.

None of our proposals are syntactic sugar with all having relevance to directing efficient code generation.