[llvm-dev] [RFC] Supporting ARM's SVE in LLVM

[Renato Golin via llvm-dev]

On 27 November 2016 at 16:51, Amara Emerson <amara.emerson at gmail.com> wrote:
> There is nothing to stop other targets from using
> stepvector/seriesvector. In fact for wide vector targets, often the IR
> constant for representing a step vector is explicitly expressed as
> <i32 0, i32 1, i32 2..> and so on (this gets really cumbersome when
> your vector length is 512bits for example). That could be replaced by
> a single "stepvector" constant, and it works the same for both
> fixed-length and scalable vectors.

Indeed! For this particular point, I think we should start there.

Also, on a more general comment regarding David's point about Hwacha,
maybe we could get some traction on the RISC-V front, to see if the
proposal is acceptable on their end, since they're likely to be using
this in the future in LLVM.

Alex, any comments?

cheers,
--renato