[llvm-dev] Prioritizing an SDNode for scheduling

[Alex Susu via llvm-dev]

   Hello, Ehsan.
     Because I use INLINEASM nodes I am not able to enforce a precise order on all the 
SelectionDAG nodes (since I can't add more chains or glues between some nodes - and even 
if I do I read that the scheduler might be able to schedule glued nodes 
non-consecutively). This has to do partly with the fact the INLINEASM "node always has two 
return values: a chain and a flag result" (from 
http://llvm.org/docs/doxygen/html/namespacellvm_1_1ISD.html).
     Given this imprecise (partial) order of the nodes I can end up with a list of machine 
instructions in the wrong order. So I need to change the order of the instructions after 
instruction selection and scheduling and I do this in [Target]AsmPrinter.cpp.

     (Note: about the bad interaction of scheduling on glued nodes you can read at
  http://lists.llvm.org/pipermail/llvm-dev/2014-June/074046.html and 
http://lists.llvm.org/pipermail/llvm-dev/2016-June/100885.html and maybe also 
http://stackoverflow.com/questions/33005061/what-are-glue-and-chain-dependencies-in-an-llvm-dag)

   Best regards,
     Alex


On 11/10/2016 1:04 AM, Ehsan Amiri wrote:
> What is the reason that you need to change the order of instructions? What is the problem
> that you want to solve?
>
> On Wed, Nov 9, 2016 at 7:05 AM, Alex Susu via llvm-dev <llvm-dev at lists.llvm.org
> <mailto:llvm-dev at lists.llvm.org>> wrote:
>
>       Hello.
>         I have tried hard, but in the end I chose a different solution: I change the order
>     of machine instructions by using the ASM writer classes such as
>     [Target]AsmPrinter.cpp. There the code is already scheduled, in a list of instructions
>     and it's very easy to move the instructions in the list.
>         (Following Ehsan's advice I looked at
>     http://llvm.org/docs/doxygen/html/classllvm_1_1GenericScheduler.html
>     <http://llvm.org/docs/doxygen/html/classllvm_1_1GenericScheduler.html> for example,
>     but I did not get any idea.)
>
>       Best regards,
>         Alex
>
>
>     On 10/21/2016 5:32 PM, Ehsan Amiri wrote:
>
>         I probably misunderstood the question. You probably want to do this in SelectionDAG.
>
>         On Fri, Oct 21, 2016 at 10:29 AM, Ehsan Amiri <ehsanamiri at gmail.com
>         <mailto:ehsanamiri at gmail.com>
>         <mailto:ehsanamiri at gmail.com <mailto:ehsanamiri at gmail.com>>> wrote:
>
>             You can do this by changing instruction scheduling heuristics. I think the more
>             important question is if this correct always for all platforms.
>
>             I don't know which scheduler you use. We use GenericScheduler and
>         PostGenericScheduler
>             before and after RA. These classes have a ::tryCandidate method which compares two
>             instructions that can be legally scheduled and decide which of the two should be
>             scheduled. Currently these method are target independent.
>
>             The correctness question still remains open for me.
>
>
>             On Thu, Oct 20, 2016 at 8:08 PM, Alex Susu via llvm-dev
>         <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
>             <mailto:llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>>> wrote:
>
>                   Hello.
>                     Is there a way to specify in the back end an (ISD::INLINEASM) SDNode to be
>                 scheduled first under all circumstances? I need to specify something like node
>                 priority to schedule the node before all other nodes in the SelectionDAG
>         of the
>                 basic block.
>                     (Using chain or glue edges in order to make a node first is not a good
>         idea,
>                 since I am doing this at instruction selection time, on individual nodes.)
>
>                   Thank you,
>                     Alex
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