[llvm-dev] MC PowerPC 32 bit vs. 64 bit

[Joerg Sonnenberger via llvm-dev]

On Tue, Nov 08, 2016 at 08:41:16AM +0100, Keve via llvm-dev wrote:
> I need to first understand why introducing the additional complexity
> (doubling the GPRs and doubling the opcodes using them) had to be
> introduced in the first place. Intuitively I would have modeled the CPU
> "by the book" with 64bit GPRs and use a flag "32bit mode" to indicate
> that upper half of the register is undefined/zero.

The mode switch effectively means that only one set of opcodes is
available at any given moment. Some architectures allow you to access
the 32bit parts of the GPRs independently (like x86), so it is natural
to model them as subregister in that case. If there is no way to access
them in parts, modelling them as independent sets makes things easier
for the register allocator.

> 32bit mode would be either hw enforced (embedded CPUs) or software
> chosen. This would allow LLVM to understand the 64bit CPUs in 32bit as
> well (SF bit of MSR).

You are assuming that it is the only difference between 32bit and 64bit
mode. In most cases, the size of pointers and registers is the smallest
part. They are typically using somewhat different ABIs, in the case of
PowerPC very different ABIs. For X86, you have instructions that only
exist in one mode or the other. The filtering works reliably on the
assembling side of things. The problem is that it seems that noone
taught the disassembler how to disambiguate things.

Joerg