[llvm-dev] sum elements in the vector

Fri May 27 20:59:56 PDT 2016

Hi Rail,

Below 2 revisions might be of your interest which Detect SAD patterns and
emit psadbw instructions on X86.:

http://reviews.llvm.org/D14840
http://reviews.llvm.org/D14897

Intrinsics related to absdiff revisons :

http://reviews.llvm.org/D10867
http://reviews.llvm.org/D11678

Hope this helps.

Regards,
Suyog

On Sat, May 28, 2016 at 4:20 AM, Rail Shafigulin via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> Hi Shahid.
>
> Do you mind providing a concrete example of X86 code where an intrinsic
> was added (preferrable with filenames and line numbers)? I'm having
> difficulty tracking down the steps you provided.
>
> Any help is appreciated.
>
>
> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad <
> Asghar-ahmad.Shahid at amd.com> wrote:
>
>> Hi Rail,
>>
>>
>>
>> We had done this for generation of X86 PSAD (sum of absolute difference)
>> instruction through
>>
>> Llvm intrinsic. Doing this requires following
>>
>> 1.       Define an intrinsic, xyz(),  for the required instruction and
>> corresponding SDNode
>>
>> 2.       Generate the “call xyz() “ IR based the matched pattern
>>
>> 3.       Map “call xyz()” IR to corresponding SDNode in
>> SelectionDagBuilder.cpp
>>
>> 4.       Provide default expansion of the xyz() intrinsic
>>
>> 5.       Legalize type and/or operation
>>
>> 6.       Provide Lowering of intrinsic/SDNode to generate your target
>> instruction
>>
>>
>>
>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details.
>>
>>
>>
>> Regards,
>>
>> Shahid
>>
>>
>>
>>
>>
>>
>>
>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail
>> Shafigulin via llvm-dev
>> *Sent:* Monday, April 04, 2016 11:00 PM
>> *To:* Das, Dibyendu
>> *Cc:* llvm-dev at lists.llvm.org
>> *Subject:* Re: [llvm-dev] sum elements in the vector
>>
>>
>>
>> Thanks for the pointers. I looked at hadd instructions. They seem to do
>> very similar to what I need. Unfortunately as I said before my LLVM
>> experience is limited. My understanding is that when I create a new type of
>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing
>> the code and is seeing a given pattern it would create this particular
>> node. I'm really struggling to understand how it is done. So here are the
>> problems that I'm having.
>>
>>
>>
>> 1. How do I identify that pattern that should be used?
>>
>> 2. How do I specify a given pattern?
>>
>>
>>
>> Do you (or someone else) mind helping me out?
>>
>>
>>
>> Any help is appreciated.
>>
>>
>>
>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com>
>> wrote:
>>
>> This is roughly along the lines of x86 hadd* instructions though the
>> semantics of hadd* may not exactly match what you are looking for. This is
>> probably more in line with x86/ARM SAD-like instructions but I don’t think
>> llvm generates SAD without intrinsics.
>>
>>
>>
>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail
>> Shafigulin via llvm-dev
>> *Sent:* Monday, April 04, 2016 9:34 AM
>> *To:* llvm-dev <llvm-dev at lists.llvm.org>
>> *Subject:* [llvm-dev] sum elements in the vector
>>
>>
>>
>> My target has an instruction that adds up all elements in the vector and
>> stores the result in a register. I'm trying to implement it in my compiler
>> but I'm not sure even where to start.
>>
>>
>>
>> I did look at other targets, but they don't seem to have anything like it
>> ( I could be wrong. My experience with LLVM is limited, so if I missed it,
>> I'd appreciate if someone could point it out ).
>>
>>
>>
>> My understanding is that if SDNode for such an instruction doesn't exist
>> I have to define one. Unfortunately, I don't know how to do it. I don't
>> even know where to start looking. Would someone care to point me in the
>> right direction?
>>
>>
>>
>> Any help is appreciated.
>>
>>
>>
>> --
>>
>> Rail Shafigulin
>>
>> Software Engineer
>> Esencia Technologies
>>
>>
>>
>>
>>
>> --
>>
>> Rail Shafigulin
>>
>> Software Engineer
>> Esencia Technologies
>>
>
>
>
> --
> Rail Shafigulin
> Software Engineer
> Esencia Technologies
>
> On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad <
> Asghar-ahmad.Shahid at amd.com> wrote:
>
>> Hi Rail,
>>
>>
>>
>> We had done this for generation of X86 PSAD (sum of absolute difference)
>> instruction through
>>
>> Llvm intrinsic. Doing this requires following
>>
>> 1.       Define an intrinsic, xyz(),  for the required instruction and
>> corresponding SDNode
>>
>> 2.       Generate the “call xyz() “ IR based the matched pattern
>>
>> 3.       Map “call xyz()” IR to corresponding SDNode in
>> SelectionDagBuilder.cpp
>>
>> 4.       Provide default expansion of the xyz() intrinsic
>>
>> 5.       Legalize type and/or operation
>>
>> 6.       Provide Lowering of intrinsic/SDNode to generate your target
>> instruction
>>
>>
>>
>> You can visit http://llvm.org/docs/ExtendingLLVM.html for details.
>>
>>
>>
>> Regards,
>>
>> Shahid
>>
>>
>>
>>
>>
>>
>>
>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail
>> Shafigulin via llvm-dev
>> *Sent:* Monday, April 04, 2016 11:00 PM
>> *To:* Das, Dibyendu
>> *Cc:* llvm-dev at lists.llvm.org
>> *Subject:* Re: [llvm-dev] sum elements in the vector
>>
>>
>>
>> Thanks for the pointers. I looked at hadd instructions. They seem to do
>> very similar to what I need. Unfortunately as I said before my LLVM
>> experience is limited. My understanding is that when I create a new type of
>> SDNode I need to specify a pattern for it, so that when LLVM is analyzing
>> the code and is seeing a given pattern it would create this particular
>> node. I'm really struggling to understand how it is done. So here are the
>> problems that I'm having.
>>
>>
>>
>> 1. How do I identify that pattern that should be used?
>>
>> 2. How do I specify a given pattern?
>>
>>
>>
>> Do you (or someone else) mind helping me out?
>>
>>
>>
>> Any help is appreciated.
>>
>>
>>
>> On Mon, Apr 4, 2016 at 9:59 AM, Das, Dibyendu <Dibyendu.Das at amd.com>
>> wrote:
>>
>> This is roughly along the lines of x86 hadd* instructions though the
>> semantics of hadd* may not exactly match what you are looking for. This is
>> probably more in line with x86/ARM SAD-like instructions but I don’t think
>> llvm generates SAD without intrinsics.
>>
>>
>>
>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Rail
>> Shafigulin via llvm-dev
>> *Sent:* Monday, April 04, 2016 9:34 AM
>> *To:* llvm-dev <llvm-dev at lists.llvm.org>
>> *Subject:* [llvm-dev] sum elements in the vector
>>
>>
>>
>> My target has an instruction that adds up all elements in the vector and
>> stores the result in a register. I'm trying to implement it in my compiler
>> but I'm not sure even where to start.
>>
>>
>>
>> I did look at other targets, but they don't seem to have anything like it
>> ( I could be wrong. My experience with LLVM is limited, so if I missed it,
>> I'd appreciate if someone could point it out ).
>>
>>
>>
>> My understanding is that if SDNode for such an instruction doesn't exist
>> I have to define one. Unfortunately, I don't know how to do it. I don't
>> even know where to start looking. Would someone care to point me in the
>> right direction?
>>
>>
>>
>> Any help is appreciated.
>>
>>
>>
>> --
>>
>> Rail Shafigulin
>>
>> Software Engineer
>> Esencia Technologies
>>
>>
>>
>>
>>
>> --
>>
>> Rail Shafigulin
>>
>> Software Engineer
>> Esencia Technologies
>>
>
>
>
> --
> Rail Shafigulin
> Software Engineer
> Esencia Technologies
>
> _______________________________________________
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> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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