[llvm-dev] sum elements in the vector

[Rail Shafigulin via llvm-dev]

On Wed, May 18, 2016 at 5:56 AM, Martin J. O'Riordan <
martin.oriordan at movidius.com> wrote:

> Hi Rail,
>
>
>
> We used a very simple pattern expansion (actually, not a pattern
> fragment).  For example, for AND, ADD (horizontal sum), OR and XOR of 4
> elements we use something like the following TableGen structure:
>
>
>
> class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType
> vt, string asmstr> :
>
>     SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),
>
>                     !strconcat(asmstr, " $dst $src"),
>
>                     [(set regVT:$dst,
>
>                       (opc (rt (vector_extract(vt VRF128:$src), 0 ) ),
>
>                         (opc (rt (vector_extract(vt VRF128:$src), 1 ) ),
>
>                           (opc (rt (vector_extract(vt VRF128:$src), 2 ) ),
>
>                             (rt (vector_extract(vt VRF128:$src), 3 ) )
>
>                           )
>
>                         )
>
>                       )
>
>                     )]>;
>
>
>
> This is okay for 4 element vectors, and it will get selected if the
> programmer writes something like:
>
>
>
> vec[0] & vec[1] & vec[2] & vec[3]
>
>
>
> but not with a simple variant like:
>
>
>
> vec[0] & vec[2] & vec[1] & vec[3]
>
>
>
> If this was properly represented by an ISD node, the other permutations
> could be more easily handled through normalisation.  We “could” write
> patterns for each of the permutations, but it is verbose, and in practice
> most people only write it one way anyway.
>
>
>
> The 8-lane equivalent has TableGen left thinking for quite a long time,
> and the 16-lane equivalent seems to hang TableGen.
>
>
>
>             MartinO
>
>
>

Just out of curiosity how do I specify multiple patterns for the same
instruction? I tried putting the pattern in the pattern list but it LLVM
complained that I can't set the same register multiple times.


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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