[llvm-dev] specify dag pattern for an instructions

[Nemanja Ivanovic via llvm-dev]

It sounds like you want to specify a target-specific DAG combine. I'm sure
most targets have many examples of this, but I'm familiar with PPC, so you
can have a look at the node ISD::SIGN_EXTEND in
lib/Target/PowerPC/PPCISelLowering.cpp. We specify in the target
constructor that there's a DAG combine for the node (
setTargetDAGCombine(ISD::SIGN_EXTEND);). Then we specify what to do with it
in PPCTargetLowering::PerformDAGCombine. Of course, the semantics are very
different from what you're trying to do, but I think the general approach
is what you're looking for (i.e. note that there's a target-specific DAG
combine, then specify the details of the combine).

I hope this helps and that I haven't misunderstood your question.
Nemanja

On Fri, May 13, 2016 at 1:05 AM, Rail Shafigulin via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> I'd like to apologize in advance if the question seems dumb, but I've
> never specified a DAG pattern for an instruction a don't know how it looks
> in LLVM.
>
> My target has an instruction which is similar to X86 horizontal add. The
> instruction, let's call is sumreduce, sums up all the elements in a vector
> and stores a result in GPR. What I'm trying to do is to replace a specific
> DAG pattern (it is given below) with this instruction (DAG node).
>
> Here is the pattern I need to replace:
>
>            r0 r1
>              \ /
>             add  r2
>                \    /
>                add  r3
>                   \    /
>                   add
>                     |
>                    r4
>
> with
>             r4 = sumreduce r0 r1 r2 r3
>
> For now assume that the vector has 4 elements in it and all of them are
> i32.
>
> I would appreciate any pointers on how to do it. If someone could point me
> to an example code that converts a DAG pattern to a DAG node I would
> greatly appreciate it.
>
>
> --
> Rail Shafigulin
> Software Engineer
> Esencia Technologies
>
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>
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