[llvm-dev] Is it possible to avoid inserting spill/split code in certain instruction sequence in RA?
Dongrui She via llvm-dev
llvm-dev at lists.llvm.org
Mon May 9 11:30:10 PDT 2016
Hi all,
I am working on an out-of-tree target. I am wondering if it is possible to
force the register allocator (and/or spiller) to not break certain
instruction sequence.
For example:
phys_reg = MI1 vreg1
vreg 2 = MI2 phys_reg
Is there a way to tell RA/spiller not to insert COPY or spill between MI1
and MI2?
I am using greedy register allocator and inline spiller.
--
Regards,
Dongrui
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