[llvm-dev] generate vectorized code
Rail Shafigulin via llvm-dev
llvm-dev at lists.llvm.org
Wed Mar 16 17:38:47 PDT 2016
On Wed, Mar 16, 2016 at 11:48 AM, Mehdi Amini <mehdi.amini at apple.com> wrote:
> Hi Rail,
>
> Two hints to begin with:
>
> 1) Makes sure you example is vectorized on X86 for example
> 2) Is your target correctly overriding the TTI (declaring the vector
> register size for example) so that the vectorizer can kicks-in (see
> X86TTIImpl::getRegisterBitWidth for instance). Alternatively you can test
> the SLP vectorizer by passing to clang: -mllvm -slp-max-reg-size -mllvm 512
> (I don't see an equivalent option for the loop vectorizer though).
>
> Well, it sort of worked. I added a getRegisterBitWidth(...) but then I got
this error:
fatal error: error in backend: Cannot select: 0x5e949a8: v4i32 =
BUILD_VECTOR 0x5e91ae8, 0x5e91ae8, 0x5e91ae8, 0x5e91ae8 [ORD=16] [ID=16]
0x5e91ae8: i32 = Constant<0> [ID=5]
0x5e91ae8: i32 = Constant<0> [ID=5]
0x5e91ae8: i32 = Constant<0> [ID=5]
0x5e91ae8: i32 = Constant<0> [ID=5]
What am I missing?
Any help is appreciated.
> --
> Mehdi
>
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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