[llvm-dev] Instructions with register constraints

[Pei-Shiang Hung via llvm-dev]

I'm porting a new LLVM target.
My ISA has an 'add333 $rd3, $rt3, $rs3 ' instruction which acts as
'add $rd5, $rt5, $rs5'.
$rd5, $rt5, and $rs5 are register operands with 5-bit encoding space,
thus  they can access register from $r0 to $r31 belong to GPR register
class.
However, $rd3, $rt3, and $rs3 are register operands with only 3-bit
encoding space; in other word, they can only access registers from $r0
to $r7 belong to the same GPR register class.
I have no idea how to describe this kind of register constraints.

Please kindly guide me the direction.
Thanks in advance.