[llvm-dev] adding vector instructions

[Rail Shafigulin via llvm-dev]

I'm trying to add vector instructions to my target. At the moment I'm
focusing on vector load. I managed to add an actual instruction but now I
need llvm to recognize the pattern and use it. This is where I facing most
of the difficulties as I have fairly poor understanding on how to define
these patterns.

What I need llvm to recognize is the followiwng

ld r1, 0(r6)
ld r3, 4(r6)
ld r2, 8(r6)
ld r5, 12(6)

as a load to a vector register, i.e

vld vr1, 0(r6)

The format of the instructions is the following

ld r1 4(r6) means load register r1 with a value stored at address r6 + 0

Does anyone know how to do it?

Any help is greatly appreciated.



-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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