[llvm-dev] Enable / Disable a processor feature

[Rail Shafigulin via llvm-dev]

I'm trying to enable/disable a target feature through clang.

Here is how my target looks like

// Esencia subtarget features
//===----------------------------------------------------------------------===//
def FeatureMul   : SubtargetFeature<"mul", "HasMul", "true",
                                   "Enable hardware multiplier">;
def FeatureDiv   : SubtargetFeature<"div", "HasDiv", "true",
                                   "Enable hardware divider">;
def FeatureCmov  : SubtargetFeature<"cmov", "HasCmov", "true",
                                    "Enable conditional move instruction">;
def FeatureAddc  : SubtargetFeature<"addc", "HasAddc", "true",
                                    "Enable add with carry instruction">;

//===----------------------------------------------------------------------===//
// Esencia processors supported.
//===----------------------------------------------------------------------===//
class Proc<string Name, SchedMachineModel Model,
           list<SubtargetFeature> Features>
 : ProcessorModel<Name, Model, Features>;

def : Proc<"esencia", EsenciaModel, [FeatureMul,
                                     FeatureDiv,
                                     FeatureCmov,
                                     FeatureAddc
                                    ]>;

This is what I have in EsenciaTargetInfo::setFeatureEnabled(...) in
clang/lib/Basic/Targets.cpp

  virtual void setFeatureEnabled(llvm::StringMap<bool> &Features,
                                 StringRef Name,
                                 bool Enabled) const {
    if (Name == "mul" ||
        Name == "div" ||
        Name == "cmov" ||
        Name == "addc") {
      Features[Name] = Enabled;
    }
  }

Is there a way to enable/disable a given feature through clang? Any flags I
need to pass?

Any help is appreciated.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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