[llvm-dev] Why not do machine instruction scheduling in SSA form?

[Xing Su via llvm-dev]

Hi LLVM community,

Currently LLVM backend do pre-RA machine instruction scheduling in non-SSA form, I doubt why not do machine scheduling in SSA machine instruction form? Now LLVM’s machine scheduling uses a list-scheduling algorithm, but if we wang to support more complex scheduling algorithms, for example, modulo scheduling for loops, it seems more easy to accomplish this in SSA form as SSA is more suitable for tracking dependencies and doing code motion.

I find that LiveIntervals analysis pass, which is required by RegPressureTracker and MachineScheduler, cannot run before phi elimination. Is this one of the reason that machine scheduling is not done in SSA form?

Any explanation is appreciated. Thanks a lot!



Cheers,
Xing