[llvm-dev] [iovisor-dev] [PATCH, BPF 5/5] BPF: Add 32-bit and pattern

[Alexei Starovoitov via llvm-dev]

On Wed, Jun 15, 2016 at 2:37 PM, Richard Henderson via iovisor-dev
<iovisor-dev at lists.iovisor.org> wrote:
> We can represent a 64-bit AND with unsigned immediate
> with a 32-bit AND opcode.
>
> Signed-off-by: Richard Henderson <rth at twiddle.net>
> ---
>  lib/Target/BPF/BPFInstrInfo.td | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/lib/Target/BPF/BPFInstrInfo.td b/lib/Target/BPF/BPFInstrInfo.td
> index 33481b9..62c2dd8 100644
> --- a/lib/Target/BPF/BPFInstrInfo.td
> +++ b/lib/Target/BPF/BPFInstrInfo.td
> @@ -273,6 +273,21 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
>    } // isMoveImm
>  }
>
> +let Constraints = "$dst = $srcd", isAsCheapAsAMove = 1, isCommutable = 1 in {
> +  def AND_ru
> +    : F_COF<4 /* BPF_ALU */, 0x5 /* BPF_AND */, 0 /* BPF_K */,
> +            (outs GPR:$dst), (ins GPR:$srcd, i64imm:$imm),
> +            "andwi\t$dst, $imm",
> +            [(set GPR:$dst, (and GPR:$srcd, i64immZExt32:$imm))]> {

nice!
Do you have further optimizations that take advantage of 32-bit
subregisters and zero extension?
Should it be added in more generic way instead of pattern match?