[llvm-dev] Is addrspace info available during instruction scheduling?

[Phil Tomson via llvm-dev]

Ah, sorry, this was operator error on my part... I do now see different
address spaces using that method.

Thanks.

Phil

On Mon, Jun 13, 2016 at 7:52 PM, Phil Tomson <phil.a.tomson at gmail.com>
wrote:

>
>
> On Mon, Jun 13, 2016 at 12:14 PM, Matthias Braun <mbraun at apple.com> wrote:
>
>> You should be able to get the related MachineInstrs (SDNode->Instr). If
>> you have different instructions for different address spaces you can just
>> check the opcode, otherwise you can check if the instructions have
>> MachineMemOperands which contains additional information about the memory
>> access including the address space involved.
>>
>
> I tried the latter suggestion since we don't have different load
> instructions for different address spaces and noticed that all of the
> address spaces that get returned are 0 - even though the .ll file shows
> loads from different addressspaces like:
>
>  %0 = load i32 addrspace(4)* @answer, align 4
>   store i32 %0, i32* @xint, align 4
>   %1 = load i32 addrspace(2)* @seven, align 4
>   store i32 %1, i32* %bint, align 4
>   %2 = load i32 addrspace(3)* @two, align 4
>
> This is what I tried:
>
> unsigned
>     XTargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
>                                            const MachineInstr *MI,
>                                            unsigned *PredCost) const {
>
>    int Latency = XTargetGenInstrInfo::getInstrLatency(ItinData, MI,
> PredCost);
>
>       std::string type_str;
>       llvm::raw_string_ostream rso(type_str);
>       MI->print(rso);
>       if(PredCost) {
>       std::cout << "    PredCost: " << *PredCost << "\n";
>       }
>          MachineInstr::mmo_iterator MMOI;
>          for(MMOI = MI->memoperands_begin(); MMOI !=
> MI->memoperands_end(); ++MMOI) {
>            std::cout << "     AddressSpace:" << ((*MMOI)->getAddrSpace())
> << "\n";
>          }
>     return Latency;
> }
>
>
> Phil
>
>
>
>> - Matthias
>>
>> > On Jun 13, 2016, at 11:55 AM, Phil Tomson via llvm-dev <
>> llvm-dev at lists.llvm.org> wrote:
>> >
>> > We'd like to be able to vary the latency of our load instructions based
>> on what address space is being loaded from. I was thinking I could do this
>> by overriding getOperandLatency in our target, but I'm wondering if the
>> addrspace info is available when instructions are scheduled?
>> >
>> > For example, I have this in our llvm IR:
>> >
>> >   %0 = load i32 addrspace(4)* @answer, align 4
>> >   store i32 %0, i32* @xint, align 4
>> >   %1 = load i32 addrspace(2)* @seven, align 4
>> >   store i32 %1, i32* %bint, align 4
>> >   %2 = load i32 addrspace(3)* @two, align 4
>> >   store i32 %2, i32* %cint, align 4
>> >
>> > Loading from addrspace(4) or addrspace(3) should have a much higher
>> latency than loading from addrspace(2) or addrspace(1).  But is that
>> information available to the instruction scheduler in our overridden
>> getOperandLatency method?
>> >
>> > Phil
>> >
>> > _______________________________________________
>> > LLVM Developers mailing list
>> > llvm-dev at lists.llvm.org
>> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>
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