[llvm-dev] Instruction Itineraries: question about operand latencies

[Phil Tomson via llvm-dev]

In our architecture loads from certain memory locations take a long time to
complete (on the order of 150 clock cycles). Since we don't have a way to
tell at compile time if the address being loaded from lies in slow or fast
memory, I've gone ahead and made all of the load numbers high, such as:

  InstrItinData< II_LOAD1,     [InstrStage<150, [AGU]>]>,

However, I see that there is another field which I haven't specified where
operand latencies are specified.  Here's an example from
ARMScheduleA8.td:

  InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>,

Now I'm wondering if Instead of what I had above, I should instead have
specified:

  InstrItinData< II_LOAD1,     [InstrStage<150, [AGU]>],[150,1,1]>,

?

but is that first '150' parameter there redundant? Since it's specified in
the operand latency list ([150,1,1] - the first element of that array being
the latency for the output)?


To clarify, for values of  'A' and 'B' below:

  InstrItinData< II_LOAD1,     [InstrStage<A, [AGU]>], [B,1,1]>,

...what is the difference in the meaning for 'A' and 'B'? Are they
essentially the same value since only one functional unit is specified?
([AGU])

Phil
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