[llvm-dev] [GSoC 2016] Parameters of a target architecture

[Roman Gareev via llvm-dev]

2016-06-03 16:41 GMT+05:00 Michael Kruse <llvmdev at meinersbur.de>:
> 2016-06-02 13:57 GMT+02:00 Roman Gareev via llvm-dev <llvm-dev at lists.llvm.org>:
>> 1. Size of double-precision floating-point number.
>
> By IEEE 754, its always 8 bytes.
>
> Generally, use DataLayout::getTypeAllocSize/getTypeStoreSize to get a
> type's size.
>
>
>> 2. Number of double-precision floating-point numbers that can be hold
>> by a vector register.
>
> TargetTransformInfo::getRegisterBitWidth (divided by 8 if double)
>
>
>> 3. Throughput of vector instructions per clock cycle.
>
> TargetTransformInfo::getArithmeticInstrCost
>
> See LoopVectorizationCostModel::getInstructionCost for how to use it.
>
>
>> 4. Latency of instructions (i.e., the minimum number of cycles between
>> the issuance of two dependent consecutive instructions).
>
> I think latency and throughput cannot be queried separately. They are
> combined as 'cost'.
>
>
>> 5. Paramaters of cache levels (size of cache lines,  associativity
>> degrees, sizes).
>
> TargetTransformInfo::getCacheLineSize
>
> That is, available for one level (probably L1 Data Cache) only. I
> think the X86 backend doesn't even define it (returns 0)
>
>
> For the information that is missing, I suggest to use command line
> options to get the information directly from the user. In the long
> term, we could add it TargetTransformInfo as well.

Thank you very much for the detailed information and ideas!

-- 
                                    Cheers, Roman Gareev.