[llvm-dev] [GSoC 2016] Parameters of a target architecture

[Roman Gareev via llvm-dev]

Dear LLVM contributors,

I work on the "Improvement of vectorization process in Polly". At the
moment I'm trying to implement tiling, interchanging and unrolling of
specific loops based on the following algorithm for the analytical
modeling [1]. It requires information about the following parameters
of a target architecture:

1. Size of double-precision floating-point number.

2. Number of double-precision floating-point numbers that can be hold
by a vector register.

3. Throughput of vector instructions per clock cycle.

4. Latency of instructions (i.e., the minimum number of cycles between
the issuance of two dependent consecutive instructions).

5. Paramaters of cache levels (size of cache lines,  associativity
degrees, sizes).

Could you please advise me where I can find such information? If I'm
not mistaken, we can get the size of a cache line and the width of the
largest vector register (which probably helps to determine the second
parameter) from TargetTransformInfo.h.

I would be very grateful for your comments, feedback and ideas.

Refs.:

[1] - http://www.cs.utexas.edu/users/flame/pubs/TOMS-BLIS-Analytical.pdf

-- 
                                    Cheers, Roman Gareev.