[llvm-dev] Instruction selection bug for vector store with FixedStack

[Alex Susu via llvm-dev]

   Hello.
     Could you please help me solve the following LLC bug happening at instruction 
selection time:
         ISEL: Starting pattern match on root node: t172: ch = store<ST64[FixedStack6]> 
t0, t6, FrameIndex:i64<6>, undef:i64

           Initial Opcode index to 157
           Skipped scope entry (due to false predicate) at index 162, continuing at 236
           Match failed at index 241
           Continuing at 263
         LLVM ERROR: Cannot select: t172: ch = store<ST64[FixedStack6]> t0, t6, 
FrameIndex:i64<6>, undef:i64
           t6: v8i64,ch = CopyFromReg t0, Register:v8i64 %vreg19
             t5: v8i64 = Register %vreg19
           t171: i64 = FrameIndex<6>
           t73: i64 = undef
         In function: foo

     I actually have difficulties in understanding in the Selection DAG what the 
FixedStack operand means. Also, it is not really clear for me how to handle it in my back end.

     Below follows and excerpt of the Selection DAG with the problem:
         Optimized legalized selection DAG: BB#16 'foo:vector.body34'
         SelectionDAG has 71 nodes:
           t0: ch = EntryToken
           t6: v8i64,ch = CopyFromReg t0, Register:v8i64 %vreg19
             t142: i64,ch = CopyFromReg t0, Register:i64 %vreg18
           t143: i64 = add t142, Constant:i64<8>
               t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64
             t173: i64,ch = load<LD8[FixedStack6](align=64)> t172, FrameIndex:i64<6>, 
undef:i64
         ...
                       t127: ch = store<ST8[%aPtr.addr74]> t105:1, t109, Constant:i64<0>, 
undef:i64
                       t106: v8i64 = add t105, t79
                     t129: ch = store<ST64[inttoptr (i64 3 to <8 x 
i64>*)](align=8)(alias.scope=<0x20c8ea0>)(noalias=<0x20c8a80>,<0x20cd700>)> t127, t106, 
Constant:i64<3>, undef:i64
         ...
         ...



   Thank you,
     Alex