[llvm-dev] Specifying DAG patterns in the instruction

[Rail Shafigulin via llvm-dev]

I'm confused about how to specify DAG patterns for a given instruction

Here is an example for my target

class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
  : ALU_RR<subOp, asmstr,
           [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;

def ADD  : ALU1_RR<0x0, "l.add", add>;

The set operation simply creates a list. The add operation creates a union.
So at the end  [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]
becomes a just a regular set. How come this is a DAG? I feel like I'm
missing something. Would anyone be able to help with the explanation?

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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