[llvm-dev] Instruction selection gives "LLVM ERROR: Cannot select"

[RCU via llvm-dev]

   Hello.
     I'm writing a back end for a RISC processor (similar to BPF) with a large SIMD unit.

     I tried in the last days to make llc compile to SIMD code the following LLVM program:
define i32 @foo(i32* %A, i32* %B, i32* %C, i32 %N) #0 {
entry: ;vector.body: ; preds = %vector.body, %vector.body.preheader.split.split
%0 = getelementptr inbounds i32, i32* %A, i64 0 ; i64 %index ; Alex: I guess this is 
useless, since offset is 0 - but we keep this redundancy
%1 = bitcast i32* %0 to <16 x i32>*
%wide.load = load <16 x i32>, <16 x i32>* %1, align 4
%2 = getelementptr inbounds i32, i32* %B, i64 0 ; i64 %index ; Alex: I guess this is 
useless, since offset is 0 - but we keep this redundancy
%3 = bitcast i32* %2 to <16 x i32>*
%wide.load17 = load <16 x i32>, <16 x i32>* %3, align 4
%4 = add nsw <16 x i32> %wide.load17, %wide.load

%5 = getelementptr inbounds i32, i32* %C, i64 0
%6 = bitcast i32* %5 to <16 x i32>*
store <16 x i32> %4, <16 x i32>* %6, align 4

%res = load i32, i32* %C, align 4
ret i32 %res
}
!llvm.ident = !{!0}
!0 = !{!"clang version 3.8.0 (trunk 253324)"}
!1 = distinct !{!1, !2}
!2 = !{!"llvm.loop.unroll.disable"}
!3 = distinct !{!3, !4, !5}
!4 = !{!"llvm.loop.vectorize.width", i32 1}
!5 = !{!"llvm.loop.interleave.count", i32 1}
!6 = distinct !{!6, !2}
!7 = distinct !{!7, !4, !5}


     I get the following error:
       LLVM ERROR: Cannot select: t21: ch = store<ST64[%6](align=4)> t20, t19, t6, undef:i64

     I don't understand why because it seems to me store is specified well in 
[MyTarget]InstrInfo.td .


     Can somebody help with an idea? Myself I will try to debug the code generated with 
TableGen, implementing the function SelectCode() .



   Best regards,
     Alex