[llvm-dev] Type inference in TableGen DAG patterns
Phil Tomson via llvm-dev
llvm-dev at lists.llvm.org
Wed Jan 13 09:59:08 PST 2016
Given the following definitions:
def SDT_XSTGMVINI : SDTypeProfile<1, 1, [SDTCisInt<0>]>;
def XSTGMVINI : SDNode<"XSTGISD::MVINI", SDT_XSTGMVINI>;
def SDT_RELADDR : SDTypeProfile<1, 2, []>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Constraints = "$dst = $addr", Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
//(ins GPRC:$spoff, GPRC:$addr),
(ins i64imm:$spoff, i64imm:$addr),
"! RELADDR $spoff, $dst",
[(set GPRC:$dst, (XSTGRELADDR
i64:$spoff,
(XSTGMVINI i64:$addr)
)
)]>;
}
When I compile I get:
XSTGInstrInfo.td:903:3: error: In RelAddr: Could not infer all types in
pattern!
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
^
I thought that perhaps I could explicitly add the type in like this:
let Constraints = "$dst = $addr", Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
//(ins GPRC:$spoff, GPRC:$addr),
(ins i64imm:$spoff, i64imm:$addr),
"! RELADDR $spoff, $dst",
[(set GPRC:$dst, (XSTGRELADDR
i64:$spoff,
i64:(XSTGMVINI i64:$addr)
)
)]>;
}
But that causes another problem:
XSTGInstrInfo.td:908:73: error: expected variable name in dag literal
i64:(XSTGMVINI i64:$addr)
^
How can this be resolved?
Phil
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