[llvm-dev] TableGen error message: top-level forms in instruction pattern should have void types

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Fri Jan 8 09:53:17 PST 2016


On 1/7/2016 5:54 PM, Phil Tomson wrote:
> I got it to compile by changing to:
> def SDT_RELADDR       : SDTypeProfile<1, 2, [SDTCisInt<0>,
> SDTCisSameAs<0, 1>]>;
> def XSTGRELADDR       : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>
> let Uses= [GRP] in {
>    def RelAddr           : XSTGPseudo< (outs GPRC:$dst),
>                                        (ins GPRC:$spoff, GPRC:$addr),
>                                        "! RELADDR $spoff, $dst",
>                                        [(set GPRC:$dst, (XSTGRELADDR
> GPRC:$addr, GPRC:$spoff))]>;
> }
>
> ...though I'm not entirely sure if it's going to do what I want.

If you want the final address to be put in the same register as the 
input, you can add a constraint "$dst = $addr":

let Uses= [GRP] in {
    def RelAddr : XSTGPseudo<(outs GPRC:$dst),
               (ins GPRC:$spoff, GPRC:$addr),
               "! RELADDR $spoff, $dst",
               [(set GPRC:$dst, (XSTGRELADDR GPRC:$addr, GPRC:$spoff))],
               "$dst = $addr">;
}


-Krzysztof

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