[llvm-dev] misheduler and register pressure tracking

[Jonas Paulsson via llvm-dev]

Hi,

SystemZ (z13) has a register file of 16 fp registers and 32 vector 
registers, where the fp registers are subregs of the first 16 vector 
registers.

The mischeduler updates current register pressure as it schedules an 
instruction. If register pressure in the fp reg class increases, so 
should the vector reg class' regressure value. However, virtual fp 
registers - no matter how many - could never use the upper 16 vector 
registers. So I am then thinking that the vector registers should not 
feel they are under pressure just because there might be many fp registers.

Checking the debug dump of mischeduler:

Bottom Pressure:
FP32Bit=18
GR32Bit=1
GRX32Bit=21
VR32Bit=18 <<<<<<<<<<<<
...
Scheduling SU(28) %vreg505<def,tied1> = SEBR %vreg505<tied0>, %vreg498, 
%CC<imp-def,dead>; FP32Bit:%vreg505,%vreg498
Bottom Pressure:
FP32Bit=19
GR32Bit=1
GRX32Bit=21
VR32Bit=19 <<<<<<<<<<<<<

The VR32Bit value keeps going up, and from what I will see it might very 
well affect scheduling of vector instructions poorly, when the VR32Bit 
regpressure set goes over its limit. It seems to me there should be some 
mechanism for how a subregclass influences a superregclass in this 
scenario.

The PressureSets for a FP32Bit virtual register are
FP32Bit, Limit: 16
VR32Bit, Limit: 32

A vector register should update both these pressure sets normally, but 
an fp register should somehow never make the VR32Bit pset go over the 
limit of 32.
Or am I missing something that will make this work anyway?

thank you

/Jonas Paulsson