[llvm-dev] enable vector instructions

[Rail Shafigulin via llvm-dev]

I'm trying to add vector instructions to my target. Does anybody know if
LLVM has an option to enable vector instructions? In other words if LLVM
sees a possible optimization where it could use a vector instruction it
would actually use it.

Any help is appreciated.

-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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