[llvm-dev] Failure to match a DAG after a minor pattern change in a custom Target

[Rail Shafigulin via llvm-dev]

On Fri, Feb 19, 2016 at 6:10 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote:
>
>>             [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32
>> immSExt16:$imm), (i32 Cond)))]> {
>>
>
> I suspect that the "set SR:$rD" is the problem here.  The Esenciasetflag
> does not have any values that can be assigned to a
> register, so it's probably this part that causes the pattern to fail.
>
>
> Tablegen creates a xxxGenDAGISel.inc file in your target's build
> directory. The "index" numbers that the debugging info shows correspond to
> the numbers in that file.  Here's an example from HexagonGenDAGISel.inc:
>
> /*28*/              OPC_Scope, 88|128,3/*472*/, /*->503*/ // 3 children in
> Scope
> /*31*/                OPC_MoveChild, 1,
> /*33*/                OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
> /*36*/                OPC_RecordChild0, // #2 = $base
> /*37*/                OPC_RecordChild1, // #3 = $offset
> /*38*/                OPC_MoveChild, 1,
> /*40*/                OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
> /*43*/                OPC_Scope, 65, /*->110*/ // 7 children in Scope
> /*45*/                  OPC_CheckPredicate, 0, // Predicate_u32ImmPred
> /*47*/                  OPC_MoveParent,
> /*48*/                  OPC_CheckType, MVT::i32,
>
> When the matcher says "false predicate at index 123", you can look at the
> line marked with /*123*/ and see exactly what predicate it was checking.
> This helps immensely with solving such problems.
>
>
> -Krzysztof
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
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>

I'm having difficulty interpreting the EsenciaGenDAGISel.inc. Specifically
the MatcherTable. I would really appreciate any help on this. Say we are
looking at the following code:

/*254*/     /*SwitchOpcode*/ 42|128,4/*554*/,
TARGET_VAL(EsenciaISD::SET_FLAG),// ->812
/*258*/       OPC_RecordChild0, // #0 = $rA
/*259*/       OPC_Scope, 99|128,2/*355*/, /*->617*/ // 2 children in Scope
/*262*/         OPC_CheckChild0Type, MVT::i32,
/*264*/         OPC_RecordChild1, // #1 = $imm
/*265*/         OPC_Scope, 59|128,1/*187*/, /*->455*/ // 2 children in Scope
/*268*/           OPC_MoveChild, 1,
/*270*/           OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/*273*/           OPC_CheckPredicate, 16, // Predicate_immSExt16
/*275*/           OPC_MoveParent,
/*276*/           OPC_MoveChild, 2,
/*278*/           OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
/*281*/           OPC_CheckType, MVT::i32,
/*283*/           OPC_Scope, 16, /*->301*/ // 10 children in Scope
/*285*/             OPC_CheckPredicate, 17, // Predicate_Esencia_CC_EQ
/*287*/             OPC_MoveParent,
/*288*/             OPC_CheckType, MVT::i32,
/*290*/             OPC_EmitConvertToTarget, 1,
/*292*/             OPC_MorphNodeTo, TARGET_VAL(Esencia::SFEQ_ri),
0|OPFL_GlueOutput,
                        1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2,
                    // Src: (Esenciasetflag:i32 GPR:i32:$rA,
(imm:i32)<<P:Predicate_immSExt16>>:$imm,
(imm:i32)<<P:Predicate_Esencia_CC_EQ>>) - Complexity = 11
                    // Dst: (SFEQ_ri:i32 GPR:i32:$rA, (imm:i32):$imm)
/*301*/           /*Scope*/ 16, /*->318*/
/*302*/             OPC_CheckPredicate, 18, // Predicate_Esencia_CC_NE
/*304*/             OPC_MoveParent,
/*305*/             OPC_CheckType, MVT::i32,
/*307*/             OPC_EmitConvertToTarget, 1,
/*309*/             OPC_MorphNodeTo, TARGET_VAL(Esencia::SFNE_ri),
0|OPFL_GlueOutput,
                        1/*#VTs*/, MVT::i32, 2/*#Ops*/, 0, 2,
                    // Src: (Esenciasetflag:i32 GPR:i32:$rA,
(imm:i32)<<P:Predicate_immSExt16>>:$imm,
(imm:i32)<<P:Predicate_Esencia_CC_NE>>) - Complexity = 11
                    // Dst: (SFNE_ri:i32 GPR:i32:$rA, (imm:i32):$imm)
/*318*/           /*Scope*/ 16, /*->335*/
/*319*/             OPC_CheckPredicate, 19, // Predicate_Esencia_CC_GTU
/*321*/             OPC_MoveParent,
/*322*/             OPC_CheckType, MVT::i32,
/*324*/             OPC_EmitConvertToTarget, 1,

what does it tell me? How do I interpret it?

I also have a question about predicates. What exactly are they? I know that
they are pattern leaves and have code associated with them. But how exactly
do they fit into the pattern matching?

Any help on this is appreciated.


-- 
Rail Shafigulin
Software Engineer
Esencia Technologies
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