[llvm-dev] Inferred MayLoad for instruction with pattern matching an intrinsic

[Mikael Holmén via llvm-dev]

Hi,

In my out-of-tree target I have a bunch of intrinsics for 
setting/getting the value of different hardware registers in my processor.

I declare my intrinsic for setting the register "cb" as

def int_phx_set_cb    : Intrinsic<[],
                                   [llvm_i16_ty],
                                   []>;

And then I have an instruction that I want to use for this intrinsic

  let Defs = [cb] in
  def set_cb: PhoenixMoveInst<
    (outs), (ins AnyReg_LTNo128:$src),
    "mv $src, cb",
    [(int_phx_set_cb AnyReg_LTNo128:$src)], cb],
    2, MV>;

Now I notice that with this setup, my "set_cb" instruction gets the 
properties "MayLoad" and "MayStore" even though it never does any 
load/store.

I suppose this is is inferred in Tablegen from the pattern, and since 
the intrinsic in the pattern has no specified property, it assumes the 
worst, i.e. that it can both load and store.

How should I do to model this better?

I want the intrinsic to survive optimizations even though it returns no 
value, so I would like to say it has some side effects, but I don't want 
my "set_cb" instructions to be seen as a load or store.

I know there are properties in Intrinsics.td but so far I'm too noob to 
realize if I can achieve what I want using them.

Thanks,
Mikael