[llvm-dev] [RFC] Lanai backend

[Jacques Pienaar via llvm-dev]

The ISA & encoding is documented in the comments and diagrams of
lib/Target/Lanai/LanaiInstrFormats.td. If that makes sense I'll add a link
to this tablegen in docs/CompilerWriterInfo.rst.

Thanks,

Jacques

On Tue, Feb 9, 2016 at 2:12 PM, Sean Silva <chisophugis at gmail.com> wrote:

> Do you have a psABI document? Or an ISA reference? Or an encoding
> reference?
>
> I know at least the encoding reference is missing for AArch64, so it's not
> a huge deal, but anything we can put in http://llvm.org/docs/
> CompilerWriterInfo.html (docs/CompilerWriterInfo.rst) would be
> appreciated.
>
> -- Sean Silva
>
> On Tue, Feb 9, 2016 at 9:40 AM, Jacques Pienaar via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> Hi all,
>>
>> We would like to contribute a new backend for the Lanai processor
>> (derived from the processor described in [1]).
>>
>> Lanai is a simple in-order 32-bit processor with:
>>   * 32 32-bit registers, including:
>>     * 2 registers with fixed values;
>>     * 4 used for program state tracking (PC, SP, FP, RCA);
>>     * 2 reserved for explicit usage by user (R10 and R11), used in
>> threading library;
>>     * Up to 4 used for argument passing;
>>     * No callee-saved registers
>>   * No floating point support
>>
>> Backend development is focused primarily on compiling C99 code (no
>> exception support). The patches implement all the parts required for code
>> generation:
>>
>> * LLVM triple: http://reviews.llvm.org/D17003
>> * Clang support: http://reviews.llvm.org/D17002
>> * MCExpr & ELF: http://reviews.llvm.org/D17008
>> * Lanai backend (lib/Target/Lanai): http://reviews.llvm.org/D17011
>>
>> We are still actively developing the backend and have many optimizations
>> in mind.
>>
>> I'll be the maintainer of this backend.
>>
>> Please leave code comments on the Phab patches, while discussing
>> high-level comments about the backend on this llvm-dev thread.
>>
>> Thanks,
>>
>> Jacques
>>
>> [1] David E. Culler, Anoop Gupta, and Jaswinder Pal Singh. 1997. Parallel
>> Computer Architecture: A Hardware/Software Approach (1st ed.). Morgan
>> Kaufmann Publishers Inc., San Francisco, CA, USA.
>>
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>>
>>
>
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