[llvm-dev] llc gives Segmentation fault at instruction selection [was Re: Instruction selection gives "LLVM ERROR: Cannot select"]

[RCU via llvm-dev]

   Hello, Tim,
     Thank you for your advice.
     Indeed, the problem with "LLVM ERROR: Cannot select" was a false predicate that 
should have been true. I solved the problem by simply making the C++ function implementing 
the TableGen predicate used in my store instruction (very similar to the selectIntAddrMSA 
predicate from the Mips back end) return true instead of false.


     But now I bumped into another serious problem: llc gives segmentation fault while 
doing instruction select on the store. More exactly, the vector store instruction (very 
similar to the MSA vector store from Mips) during selection gets modified during the 
combine or lowering (I guess) and when instruction selection reaches the store it has one 
input that is NULL (hence the segfault). More exactly, if we use GDB we see that at the 
i-sel of the store we have:
    ┌──/home/asusu/LLVM/llvm38Nov2016/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    │858       /// Initialize the operands list of this with N operands.│
    │859       void InitOperands(SDUse *Ops, const SDValue *Vals, unsigned N) {│
    │860         for (unsigned i = 0; i != N; ++i) {│
    │861           Ops[i].setUser(this);│
   >│862           Ops[i].setInitial(Vals[i]);│
    │863         }

  Here N = 4 and the Ops are:
   {Val = {Node = 0x6e5610, ResNo = 0}, User = 0x6e6940, Prev = 0x6e5640, Next = 0x0}
   {Val = {Node = 0x0, ResNo = 0}, User = 0x6e6940, Prev = 0x0, Next = 0x0} <-- THIS IS 
THE PROBLEM, the reason for segfault. (in frame 2 we do *this, where this is Ops[1])
   {Val = {Node = 0x6e6940, ResNo = 7231040}, User = 0x0, Prev = 0x0, Next = 0x0}
   {Val = {Node = 0x6e6940, ResNo = 7236320}, User = 0x0, Prev = 0x0, Next = 0x0}}
  (gdb) print Vals[1]
$2 = {Node = 0x0, ResNo = 0}
  (gdb) print Vals[2]
$3 = {Node = 0x0, ResNo = 0}
(gdb) print Vals[3]
$4 = {Node = 0x6c18b0, ResNo = 0}

  Before i-sel started, store had as inputs a TokenFactor, an add, a CopyFromReg (I can 
provide the entire DOT output with -view-isel-dags) and an undef. If we give during i-sel, 
at InitOperands():
   (gdb) print Ops[0].Val.Node->dump()t19: v8i64 = add t18, t17
        So, Ops[0] is add.

   So, the problem is that after instruction selection of a RET, CopyToReg and TokenFactor 
I have a messed-up SelectionDAG, with the problems mentioned above for the select 
instruction that cause the segfault.

   Did anybody encounter a similar problem before?


   Thank you,
     Alex




On 1/26/2016 1:15 AM, Tim Northover wrote:
> On 25 January 2016 at 14:52, RCU via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>      I don't understand why because it seems to me store is specified well in
>> [MyTarget]InstrInfo.td .
>>
>>      Can somebody help with an idea? Myself I will try to debug the code
>> generated with TableGen, implementing the function SelectCode() .

>>      I get the following error:
>>        LLVM ERROR: Cannot select: t21: ch = store<ST64[%6](align=4)> t20, t19, t6,
undef:i64
>>
>>      I don't understand why because it seems to me store is specified well in
>> [MyTarget]InstrInfo.td .
>>
>>
>>      Can somebody help with an idea? Myself I will try to debug the code generated with
>> TableGen, implementing the function SelectCode() .

>
> We'd need to see at least the pattern in your .td file. More of the
> DAG would also be helpful (try "llc -debug") since we've got not idea
> what t20, t19 or t6 are.
>
> About all I can suggest at the moment is following each step of the
> "llc -debug" output while it's trying to select this store, referring
> to build/lib/Target/MyTarget/MyTargetGenDAGISel.inc. You should be
> able to work out which predicate on the way to the instruction you
> expected to be used failed, which often makes it obvious what was
> wrong with the pattern.
>
> Cheers.
>
> Tim.
>