[llvm-dev] TableGen - Help to implement a form of gather/scatter operations for Mips MSA

[Simon Dardis via llvm-dev]

Hi Alex,

The operations you refer to are part of an extension to MIPS called VMIPS for teaching purposes.

The MIPS MSA ASE does not define vector scatter/gather instructions. As Daniel points out in his reply, it's
possible to simulate vector scatter/gather operations through combinations of shuffles, interleaves or just plain
GPR loads/stores combined with cross register bank copies.

I haven't looked at implementing any sort of vector scatter/gather style optimizations for MIPS yet.

Thanks,
Simon
________________________________________
From: llvm-dev [llvm-dev-bounces at lists.llvm.org] on behalf of Alex Susu via llvm-dev [llvm-dev at lists.llvm.org]
Sent: 09 December 2016 01:52
To: llvm-dev
Subject: [llvm-dev] TableGen - Help to implement a form of gather/scatter operations for Mips MSA

   Hello.
     I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and
scatter operations exist for Mips, named LVI and SVI, respectively.

     Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector
instructions) gather and scatter operations?
     If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE,
but it doesn't seem to be trivial. Also, LLVM seems to have implemented scatter/gather
instructions only for the x86 processor - there, they defined new SDNodes called
GatherNode and ScatterNode.)

   Thank you,
     Alex
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