[llvm-dev] Immediate operand for vector instructions
Alex Susu via llvm-dev
llvm-dev at lists.llvm.org
Sat Dec 3 14:42:34 PST 2016
Hello.
I have problems specifying vector instructions with immediate values in TableGen.
I wrote the following specification (I got inspired from the MSA vector instructions
for the Mips back end):
class MSA_I16_FMT<bits<9> opcode>: MSAInst {
bits<16> s16;
let Inst{31-23} = opcode;
let Inst{26-11} = s16;
}
class REP_1R_DESC_BASE<,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
/* From include/llvm/Target/Target.td:
let OperandType = "OPERAND_IMMEDIATE" in {
...
def i64imm : Operand<i64>; */
dag InOperandList = (ins i64imm:$imm);
string AsmString = "REPEAT_X_TIMES($imm";
list<dag> Pattern = [(int_repeat_x_times i64imm:$imm)];
InstrItinClass Itinerary = itin;
}
class REP_D_DESC : REP_1R_DESC_BASE;
class REP_D_ENC : MSA_I16_FMT<0b101010111>;
def REP_D: REP_D_ENC, REP_D_DESC;
and added in the LLVM program (programmatically, in an LLVM pass) an LLVM IR
repeat_x_times intrinsic.
To my big surprise (because of the property OperandType = "OPERAND_IMMEDIATE"), the
resulting ASM codegen'ed by the instruction selector contains a mov and use a register:
mov r1, 32767 // <MCInst #75 MOV_ri
// <MCOperand Reg:2>
// <MCOperand Imm:32767>>
REPEAT_X_TIMES(r1);
...
Note that in the end I managed to fix this problem by using an address operand as
immediate operand (inspired again from Mips MSA vector instructions), but I consider this
a somewhat strange solution:
class REP_1R_DESC_BASE<Operand MemOpnd = uimm4_ptr,
ImmLeaf Addr = immLeaf,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins MemOpnd:$addrdst);
string AsmString = "REPEAT_X_TIMES($addrdst );";
list<dag> Pattern = [(int_connex_repeat_x_times Addr:$addrdst)];
InstrItinClass Itinerary = itin;
}
So, is there are way to use immediate values that are not memory operands?
Thank you ,
Alex
More information about the llvm-dev
mailing list