[llvm-dev] Basic Backend: Load Indirect

[Gschwandtner Georg - S1310567008 via llvm-dev]

Hi,
I am Georg, a student for Embedded System Design at the University of Applied Sciences Upper Austria, Campus Hagenberg. (https://www.fh-ooe.at/en/hagenberg-campus/studiengaenge/master/embedded-systems-design/)
In some lectures at my university, a simple 16-bit CPU with a very small instruction set of only 24 instructions called PROL16 is used to teach CPU architecture and chip design.

I currently try to create a LLVM backend support for the PROL16 as part of a compiler example for my professor.
I started to use your LEG CPU framework(https://github.com/frasercrmck/llvm-leg/blob/master/lib/Target/LEG/) as base for the PROL16 as it is much simpler than the CPU0.
I put some time into implementing the Load/Store from/to Memory instruction.
In difference to the LEG Load/Store or most other CPUs, the PROL16 does not support an indirect memory load with an immediate.
So in LEG single instruction command like
ldr r5, sp #8
would result in a PROL16 Code more like this:
mov r4,#8 // no immediate support for arithmetic or logic instructions, therefore load the constant first into a register
add r4, r4, sp // calc the memory address
ldr r5, r4 // load indirect from memory address in r4 to register
I looked into other backends, eg. AVR or CPU0.

I found out that most likely the main topic is to adapt the SelectAddr function in LEGISelDAGToDAG.cpp so the offset it not used anymore.
I do not know how to solve this.
Does someone have a hint for me? I would very much appreciate it.

Best regards
Georg

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