[llvm-dev] Help with ISEL matching for an SDAG

[Krzysztof Parzyszek via llvm-dev]

The MergeInputChains operation verifies if the chains that are inputs to 
this node can converge to this point. When it fails, it's usually 
because it would create a cycle in the DAG.

-Krzysztof


On 7/29/2016 12:57 PM, Nemanja Ivanovic via llvm-dev wrote:
> I have the following selection DAG:
> SelectionDAG has 9 nodes:
>   t0: ch = EntryToken
>     t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
>   t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8>
> t0, t2, undef:i64
>     t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16,
> t16, t16, t16, t16, t16, t16, t16, t16
>   t11: ch,glue = CopyToReg t0, Register:v16i8 %V2, t15
>   t12: ch = PPCISD::RET_FLAG t11, Register:v16i8 %V2, t11:1
>
> and the following pattern that I'd like to match:
>
> def ScalarLoads {
>   dag Li8 =  (i32 (extloadi8 xoaddr:$src));
> }
>
>   def : Pat<(v16i8 (build_vector ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8,
>                                  ScalarLoads.Li8, ScalarLoads.Li8)),
>             (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>;
>
> But it doesn't match it. The matching fails at an index that corresponds
> to the following line:
> OPC_EmitMergeInputChains, 16, 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> 14, 15, 16,
>
> I don't know what that line means. Can someone help?
> Thanks.
>
>
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