[llvm-dev] [Sparc] builtin setjmp / longjmp - need help to get past last problem

[Chris Dewhurst via llvm-dev]

Chris Dewhurst via llvm-dev <llvm-dev <at> lists.llvm.org> writes:

> 
> Chris.Dewhurst via llvm-dev <llvm-dev <at> lists.llvm.org> writes:
> 
> > 
> > However, when compiling for Sparc, I get a "Not supported instr" for 
> the instruction EH_SjLj_Setup. Of course, it doesn't exist in reality, 
> but neither does it for PowerPC, so I can't understand why there's a 
> difference between how it's handled for the
> >  two targets.
> 
> (Having found the answer to my own question, in case it helps others 
at 
> any time)
> 
> The difference is that the PowerPC version specifies "isCodeGenOnly = 
1" 
> for *all* it's Pseudo instructions. For the Sparc version, you need to 
> specify this just for EH_SjLj_Setup instruction to avoid it being 
> optimised-away by the tablegen compiler.
> 

Sorry: I found that my test was giving me a false-positive on this. It's 
nearly correct though.

In addition to isCodeGenOnly, you need to *not* have the isPseudo flag 
set for the instruction. The PowerPC code is somewhat contradictory in 
this in that the instruction is marked as being type "Pseudo", but for 
PPC, this actually doesn't set the "isPseudo = 1" flag.

The best way to resolve this for Sparc is to simply use the InstSP 
tablegen class instead, in a construct similar to this:

let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
  def EH_SjLj_Setup : InstSP<(outs), (ins brtarget:$ptr),
                        "#EH_SjLj_Setup\t$ptr", []>,
                        Requires<[Is32Bit]>;
}

> > 
> 
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