[llvm-dev] How to get started with instruction scheduling? Advice needed.

[Phil Tomson via llvm-dev]

I notice from looking at ARMScheduleA9.td that there seems to be a hybrid
approach where they still have itineraries but also use SchedMachineModel:

//
===---------------------------------------------------------------------===//
// The following definitions describe the simpler per-operand machine model.
// This works with MachineScheduler and will eventually replace itineraries.

class A9WriteLMOpsListType<list<WriteSequence> writes> {
  list <WriteSequence> Writes = writes;
  SchedMachineModel SchedModel = ?;
}

// Cortex-A9 machine model for scheduling and other instruction cost
heuristics.
def CortexA9Model : SchedMachineModel {
  let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
  let MicroOpBufferSize = 56; // Based on available renamed registers.
  let LoadLatency = 2; // Optimistic load latency assuming bypass.
                       // This is overriden by OperandCycles if the
                       // Itineraries are queried instead.
  let MispredictPenalty = 8; // Based on estimate of pipeline depth.

  let Itineraries = CortexA9Itineraries;

  // FIXME: Many vector operations were never given an itinerary. We
  // haven't mapped these to the new model either.
  let CompleteModel = 0;
}

I'm guessing this is probably the way forward for my case since Itineraries
seem to be already mostly defined.

Phil

On Wed, Apr 20, 2016 at 1:27 PM, Phil Tomson <phil.a.tomson at gmail.com>
wrote:

> So if I use the SchedMachineModel method, can I just skip itineraries?
>
> Phil
>
> On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org>
> wrote:
>
>> Target does make a difference. VLIW needs more hand-holding. For what you
>> are describing it should be fairly simple.
>>
>>
>>
>> Best strategy – see what other targets do. ARM might be a good start for
>> generic superscalar. Hexagon for VLIW style scheduling.
>>
>>
>>
>> Depending on what you decide, you might need different target hooks.
>>
>>
>>
>> Sergei
>>
>>
>>
>> ---
>>
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
>> by The Linux Foundation
>>
>>
>>
>> *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Phil
>> Tomson via llvm-dev
>> *Sent:* Wednesday, April 20, 2016 12:51 PM
>> *To:* LLVM Developers Mailing List <llvm-dev at lists.llvm.org>
>> *Subject:* [llvm-dev] How to get started with instruction scheduling?
>> Advice needed.
>>
>>
>>
>> I need to add instruction scheduling for a new target which is a fairly
>> simple in-order execution machine.
>>
>> I've been watching this presentation from a 2014 LLVM dev meeting as it
>> seems relevant:
>>
>> "SchedMachineModel: Adding and Optimizing a Subtarget"
>> http://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf
>>
>> In this presentation the author says that there have been several ways to
>> approach scheduling in LLVM over the years:
>>
>>    - Pre 2008: SelectionDAGISel pass creates the ScheduleDAG from the
>>    SelectionDAG at the end of instruction selection
>>    - ScheduleDAG works on SelectionDAG Nodes (SDNodes)
>>    - Circa 2008: Post Register
>>
>> Allocation pass added for
>>
>> instruction selection ( SchedulePostRATDList
>>
>> works on MachineInstrs)
>>
>>    - Circa 2012: MIScheduler
>>
>> (ScheduleDAGMI) added as
>>
>> separate pass for pre-RA
>>
>> scheduling
>>
>>    - Circa 2014: MIScheduler
>>
>> adapted to optionally replace
>>
>> PostRA Scheduler
>>
>> In the presentation he goes with defining a subclass of SchedMachineModel
>> in the schedule .td file. And apparently with this approach there are no
>> instruction itineraries.
>>
>> So I'm wondering: what's the current recommended way to approach this and
>> does it depend on the type or target? (in-order, superscalar, out of order,
>> VLIW...)?
>>
>> Someone earlier started to define instruction itineraries for our target.
>> Should I continue down this road or move over to the SchedMachineModel
>> approach? Are there other recommended presentations/documents that I should
>> be looking at?
>>
>>
>>
>> Thanks.
>>
>> Phil
>>
>
>
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