[llvm-dev] Inserting MachineInstr's

[Chris.Dewhurst via llvm-dev]

Hi,

I'm nearly there and, notwithstanding that it might be better to use setOperationAction (as indicated, James), this is representative of a class of problem that I'm trying to resolve in a few places, so I'll keep onto the original question, rather than re-framing it for a different problem.

The initial problem I posted for was with the iterator, which I needed to move onwards before removing the initial instruction. That is now OK and I have this working.

I belive my problem is now with registers. The code below runs well, but when it comes to outputting instructions it fails again. I believe this is a problem with using a virtual rather than a physical register, but I'm really not sure how or where to resolve this. Any help appreciated.

The bug in the instruction printer is:
static const char* llvm::SparcInstPrinter::getRegisterName(unsigned int): Assertion `RegNo && RegNo < 153 && "Invalid register number!"' failed.

RegNo = 0x8000000, which indicates a virtual register if I understand correctly.

The code I'm using to generate the new MI is below. This works fine, except that it produces instructions that later fail as indicated above:

bool MyPass::runOnMachineFunction(MachineFunction& MF)
{
  Subtarget = &MF.getSubtarget<SparcSubtarget>();
  const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
  const TargetRegisterInfo* TRI = Subtarget->getRegisterInfo();
  const TargetRegisterClass* DoubleRC = TRI->getRegClass(SP::DFPRegsRegClassID);

  bool Modified = false;
  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI)
  {
    MachineBasicBlock &MBB = *MFI;
    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI)
    {
      MachineInstr &MI = *MBBI;

      //MI.print(errs());
      unsigned Opcode = MI.getOpcode();
      if (Opcode == SP::FMULS)
      {
        MachineRegisterInfo& MRI = MF.getRegInfo();
        unsigned int f0 = MRI.createVirtualRegister(DoubleRC);
        MachineBasicBlock::iterator NMBBI = std::next(MBBI);
        MachineOperand& MOx = MI.getOperand(0);
        DebugLoc DL = MBBI->getDebugLoc();
        BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD), f0).addReg(MOx.getReg());
        // And so on for the other new instructions.
        MI.eraseFromParent();
        MBBI = NMBBI;
        Modified = true;
      }
    }
  }

  return Modified;
}
________________________________________
From: James Y Knight [jyknight at google.com]
Sent: 08 September 2015 06:00
To: Chris.Dewhurst; Chris.Dewhurst via llvm-dev
Subject: Re: [llvm-dev] Inserting MachineInstr's

On Sep 7, 2015, at 9:40 PM, Chris.Dewhurst via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> Hi,
>
> I have a task to complete and I’m getting stuck. I can’t find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies.
>
>   Replace:
>   fmuls %f20,%f21,%f8
>
>   with the sequence:
>   fstod %f20,%f0
>   fstod %f21,%f2
>   fmuld %f0,%f2,%f8

Are you sure you need to actually do this as a post-processing pass after code generation? Why not setOperationAction(ISD::FMUL, MVT::i32, Promote);  SparcISelLowering.cpp? I believe that'd avoid having it get generated in the first place (although I've not tested it).

Also: which erratum are you trying to work around? UT699's "FMULS precision loss after FDIVD/FSQRTD"? If so, I'd think that the workaround option of adding a "std %fNN, [%sp-8]" after fdivd/fsqrtd instructions may be better?