[llvm-dev] Inserting MachineInstr's

Mehdi Amini via llvm-dev llvm-dev at lists.llvm.org
Mon Sep 7 18:52:03 PDT 2015


> On Sep 7, 2015, at 6:40 PM, Chris.Dewhurst via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Hi,
>  
> I have a task to complete and I’m getting stuck. I can’t find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I’ll not go into why: That would take the discussion away from the essential problem. E.g.
>  
>   Replace:
>  
>   fmuls %f20,%f21,%f8
>  
>   with the sequence:
>  
>   fstod %f20,%f0
>   fstod %f21,%f2
>   fmuld %f0,%f2,%f8
>  
> This is for a Sparc derived back-end and I’m already at the MachineInstr phase. The essential code I have now is as follows, but it doesn’t work. I’ve had much larger pieces of code, but I believe my mistake lies somewhere in here. I’m not sure if I’m heading down the right path with this. Please, any help would be appreciated – or any reference to an example, even better.
>  
> [code is iterating through the MachineBasicBlock – this code is pretty straightforward and you can probably guess what’s in it]
>     if (Opcode == SP::FMULS)
>       {
>         MachineOperand& MO = MI.getOperand(0);
>         DebugLoc DL = MBBI->getDebugLoc();
>         BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD), MO.getReg());


Looks like this MI will write to the final destination register (%f8 in your example), which is not what you want IIUC.

You need to create a new register for the double (%f0) using:

    const TargetRegisterClass *DoubleRC = ….
    unsigned f0 = MRI.createVirtualRegister(DoubleRC);
    unsigned f2 = MRI.createVirtualRegister(DoubleRC);


And then you can try to build your sequence with something that will look like:

        BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD), f0).addReg(MI.getOperand(1).getReg());
        BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD), ).addReg(MI.getOperand(2).getReg());
        BuildMI(MBB, MBBI, DL, TII.get(FMULD), MO.getReg()).addReg(f0).addReg(f2);

>            [ Then we’d do the second fstod and the fmuld, but I’ve not included this because the basic problem of generating the MachineInstr has happened already for this first MachineInstr]

(You haven’t really described what problem you have though).

— 
Mehdi




>         MI.eraseFromParent();
>       }
>  
> Chris Dewhurst,
> University of Limerick, Ireland
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