[llvm-dev] POssible bug in the Arm code generator

[Denis Protivensky via llvm-dev]

Hi Erik,
> GHC does not generate or use thumb instructions
 From you assembly dump, looks like the instructions are 2 bytes long, 
meaning it's Thumb code not ARM.

- Denis.
> Owen Shepherd wrote:
>
>> Pay closer attention to the instruction descriptions on the page you linked
>> above:
>>
>> LDR{*type*}{*cond*}*Rt*, [*Rn*  {, #*offset*}]        ; immediate offset
>>
>> LDR{*type*}{*cond*}*Rt*, [*Rn*, #*offset*]!          ; pre-indexed
>>
>>
>> The pre-indexed form is always specified with an offset, and* follows the
>> brackets with an exclamation mark*. You have an immediate offset load, for
>> which Rt==Rn is permitted.
> Ah, missed that.
>
>> A possible reason for an illegal instruction exception is that you have
>> generated some ARM code and tried to execute it as Thumb or vise-versa.
> Well, I'm getting SIGILL, but GHC does not generate or use thumb instructions
> and the SIGILL happens after susccessfuly running a bunch of other arm
> instructions. From GDB:
>
>    Program received signal SIGILL, Illegal instruction.
>    0x03ff9dbc in stg_ap_v_fast ()
>    (gdb) bt
>    #0  0x03ff9dbc in stg_ap_v_fast ()
>    #1  0x03fc6ce6 in StgRun (f=0x3ff9db4 <stg_ap_v_fast>, basereg=0x49d2090 <MainCapability+16>) at
>        rts/StgCRun.c:81
>    #2  0x03fca52a in schedule (initialCapability=0x49d2080 <MainCapability>, task=0x49e62c0) at
>        rts/Schedule.c:524
>    #3  0x03fcc5e6 in scheduleWaitThread (tso=0xb6c07000, ret=0x0, pcap=0xbeffeb74) at
>        rts/Schedule.c:2429
>    #4  0x03fbc7e4 in rts_evalLazyIO (cap=0xbeffeb74, p=0x402d470 <ZCMain_main_closure>, ret=0x0) at
>        rts/RtsAPI.c:500
>    #5  0x03fce2be in hs_main (argc=3, argv=0xbeffed64, main_closure=0x402d470 <ZCMain_main_closure>,
>        rts_config=...) at rts/RtsMain.c:64
>    #6  0x00141508 in main ()
>    (gdb) disassemble
>    Dump of assembler code for function stg_ap_v_fast:
>       0x03ff9db4 <+0>:     push    {r7, lr}
>       0x03ff9db6 <+2>:     sub     sp, #32
>       0x03ff9db8 <+4>:     add     r7, sp, #0
>       0x03ff9dba <+6>:     ldr     r3, [pc, #508]  ; (0x3ff9fb8 <stg_ap_v_fast+516>)
>    => 0x03ff9dbc <+8>:     ldr     r3, [r3, #0]
>       0x03ff9dbe <+10>:    and.w   r3, r3, #3
>
>
> Erik
> -- 
> ---------------------------------------------------------------------- 
> Erik de Castro Lopo http://www.mega-nerd.com/
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