[llvm-dev] what can cause a "CPU table is not sorted" assertion

[Rail Shafigulin via llvm-dev]

I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase
I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've
created an initial MyTargetSchedule.td

def MyTargetModel : SchedMachineModel {
  // HW can decode 2 instructions per cycle.
  let IssueWidth = 2;
  let LoadLatency = 4;
  let MispredictPenalty = 16;

  // This flag is set to allow the scheduler to assign a default model to
  // unrecognized opcodes.
  let CompleteModel = 0;
}

def WriteALU : SchedWrite;
def WriteBranch : SchedWrite;

let SchedModel = MyTargetModel in {
// SLOT0 can handles everything
def Slot0 : ProcResource<1>;
// SLOT1 can't handles branches
def Slot1 : ProcResource<1>;

// Many micro-ops are capable of issuing on multiple ports.
def SlotAny  : ProcResGroup<[Slot0, Slot1]>;

def : WriteRes<WriteALU, [SlotAny]> {
  let Latency = 1;
  let ResourceCycles =[1];
}

def : WriteRes<WriteBranch, [Slot0]> {
  let Latency = 1;
  let ResourceCycles =[1];
}
}

I've also changed OR1K.td to have

def : ProcessorModel<"generic", MyTargetModel, [FeatureDiv, FeatureMul]>;
def : ProcessorModel<"or1200",  MyTargetModel, [FeatureDiv, FeatureMul]>;


No issues compiling the code. But when I run the following command I get
and assertion:

llc -mcpu=mytarget hello_world.compiled.ll -debug-only=misched
-mtriple=mytarget-unknown-linux-gnu

This
<https://github.com/openrisc/llvm-or1k/blob/master/lib/MC/SubtargetFeature.cpp#L268>is
the offending line.

I'd really appreciate if someone could point out the problem.

Thanks,

-- 
Rail Shafigulin
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