[llvm-dev] backend define a register with multiple types

[Xiangyang Guo via llvm-dev]

Please ignore my previous email. I find the error is due to a typo in my
code. In ADDFLOAT should use 'fadd' instead of 'add' for pattern matching.

2015-10-14 0:06 GMT-04:00 Xiangyang Guo <eceguo at gmail.com>:

> Hi,
>
> I want to define a register with multiple types for a particular backend.
> I checked the RegisterInfo.td for ARM backend, which covers this case. I
> tried to do the similar thing but I got errors when I build the backend.
>
> I did this as following:
>
> In the RegisterInfo.td, I define the register class like this:
>
> *def GRRegs : RegisterClass<"FOO", [i32, f32], 32, (add R0, R1, R2, R3)>;*
>
> In the InstrInfo.td, I define the instruction like this:
>
> *def ADDINT: InstFOO<(outs GRRegs:$dst),*
> *                   (ins GRRegs:$src1, GRRegs:$src2),*
> *                   "add-int $dst, $src1, $src2",*
> *                   [(set i32:$dst, (add i32:$src1, i32:$src2))]>;*
>
> *def ADDFLOAT: InstFOO<(outs GRRegs:$dst),*
> *                   (ins GRRegs:$src1, GRRegs:$src2),*
> *                   "add-float $dst, $src1, $src2",*
> *                   [(set f32:$dst, (add f32:$src1, f32:$src2))]>;*
>
> Then when I build the backend, it gives me this error:
> *error: In ADDFLOAT: Type inference contradiction found, merging 'i32'
> into 'f32'*
>
> I appreciate if if anyone can point out my errors or give me any
> suggestions to make a register with multiple types works?
>
> Regards,
>
> Xiangyang
>
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