[llvm-dev] Per-write cycle count with ReadAdvance

[Pierre-Andre Saulais via llvm-dev]

Hi all,

I am working on a backend that uses the ProcResource scheduling model 
and one limitation I found is that while it is possible to specify 
multiple SchedWrites in a ReadAdvance record, each write uses the same 
cycle count. I tried writing multiple ReadAdvance records for the same 
SchedRead, but tablegen does not seem to allow that.

It would be useful to have a per-write cycle count to model different 
pipeline bypasses, where the cycle count depends on the (read, write) 
pair and not just on the read.

Two possible solutions are: 1) changing the 'Cycles' field in 
(Proc)ReadAdvance to be a list of int and 2) changing tablegen to allow 
multiple (Proc)ReadAdvance records with the same read resource.

The former solution doesn't seem ideal as it requires repeating the 
cycle count many times for targets that use long SchedWriteRes lists:

-def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
+def: ReadAdvance<ReadIM, [1, 1, 1, 1, 1, 1, 1, 1], [WriteImm, WriteI,
                                WriteISReg, WriteIEReg,WriteIS,
                                WriteID32,WriteID64,
                                WriteIM32,WriteIM64]>;

The latter is a bit more verbose when per-write cycle count is used, but 
requires no change to existing targets. It is also easier to visually 
match cycle counts to write types:

def : ReadAdvance<ReadFoo, 2, [WriteType1]>;
def : ReadAdvance<ReadFoo, 4, [WriteType2]>;
def : ReadAdvance<ReadFoo, 3, [WriteType3]>;

I have a patch for the second solution. Would that benefit any in-tree 
target?

Thanks,
Pierre-Andre

-- 
Pierre-Andre Saulais
Principal Software Engineer, Compilers
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