[llvm-dev] Obtaining llvm::Target::OpTypes from MCInstrDesc

Tom Stellard via llvm-dev llvm-dev at lists.llvm.org
Wed Nov 25 08:20:36 PST 2015


On Wed, Nov 25, 2015 at 05:56:50PM +0200, Alexandru Guduleasa via llvm-dev wrote:
> Hi all,
> 
> I've noticed that tablegen can generate a list with enums for all the
> operands in InstrInfo.inc, such as:
> 
> #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
> #undef GET_INSTRINFO_OPERAND_TYPES_ENUM
> namespace llvm {namespace Cpl {
> namespace OpTypes {
> enum OperandType {
> ...
>   s5Imm = 10,
> ...
> 

It doesn't look like anything in-tree is using this.  However, the
AMDGPU backend uses a different approach to solving this problem.
You can set the OPERAND_TYPE string to a target specific value, and
this will be stored in the MCOperandInfo structure.

For examples, search for OPERAND_REG_INLINE_C in the AMDGPU backend.

-Tom

> I can't figure out how to obtain this enum from a particular instruction.
> What I'm trying to do is figure out the number of bits that I can use
> for encoding an immediate value.
> 
> In the FoldImmediate method, assuming that I have an ADD instruction
> and an immediate value, I want to change the ADD to an ADDI
> instruction, but before I can do this I need to make sure the
> immediate will fit.
> 
> Is there a way to obtain the OperandType for an operand?
> If I know that the OperandType is 's5Imm', I know that I can encode a
> signed value, in 5 bits.
> 
> Or maybe I'm trying to approach this in a wrong way.
> If that's the case, any help is appreciated.
> 

Hi,

There are several examples in the AMDGPU backend of how to do this.

> Best regards,
> Alex Guduleasa
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