[llvm-dev] Help making 'narrow instruct microcode' Backend

[Pekka Jääskeläinen via llvm-dev]

Hi James,

On 11/24/2015 07:40 PM, James R. Byerly via llvm-dev wrote:
> My target has a lot in common with VLIW architectures, except for the 'VL'
> part. I'd like to essentually have similar low-level semantics without
> bundling instructions in order to take advantage of the llvm scheduling
> and register allocation capabilities (and also make the target simpler,
> not having to perform any but the simplest operations).

I wonder if you already know about Transport Triggered Architectures?
Their programming model seems very close to your microcode approach.

You might be interested to take a look at TTA or exposed/explicit
datapath architectures in general, and our related TCE toolset work.

I wrote a blog about TCE and LLVM some 5y ago:

http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html

There's an open source release of TCE which has been used widely in
academia and also in some commercial designs.

We utilize LLVM for big part of the compiler, but have our own final
code gen / isched steps due to the unconventional programming model.

HTH,
-- 
Pekka