[llvm-dev] Hexagon, DFAPacketizer and instruction expansion

[Rail Shafigulin via llvm-dev]

On Fri, Nov 20, 2015 at 2:20 AM, Bruce Hoult <bruce at hoult.org> wrote:

> Sorry to butt in .. but curious ...
>
> "a RET instruction which gets expanded into a write to a register and a
> jump/branch"
>
> If you do that after Register Allocation then where do you get the
> temporary register from? Not knowing the architecture in question at all,
> maybe there's a dedicated one, in which case fine. But if not?
>

I was wrong. This was an assumption as I didn't know where I can check it.
Turns out it expand only to a jump instruction.


-- 
R
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